Anand Raghunathan

Anand Raghunathan photo

Dr. Raghunathan is a Professor in the School of Electrical and Computer Engineering at Purdue. Before joining Purdue, he was a Senior Research Staff Member and Project Leader at NEC Labs America, where he led research and technology transfer efforts in the areas of System-on-chip design, secure embedded computing, and design methodology. He received M.A. and Ph.D. degrees from Princeton University and a B.Tech. degree from the Indian Institute of Technology, Madras. Prof. Raghunathan received eight best-paper awards at premier IEEE and ACM conferences, and two Technology Commercialization awards and a Patent of the Year award from NEC Labs. He received the TR35 award from MIT (given to 35 young innovators worldwide across all areas of science and technology) for his contributions to “making mobile secure”. He is a Fellow of the IEEE and Golden Core member of IEEE Computer Society. He has chaired three premier IEEE conferences and served on several IEEE/ACM conference Technical Program Committees and journal Editorial Boards. Prof. Raghunathan’s research at Purdue focuses on computing with post-CMOS devices [1-3], domain-specific processing for emerging workloads such as recognition and data mining, energy-efficient design, and heterogeneous parallel computing. Prof. Raghunathan has published a book, eight book chapters, over 190 refereed conference and journals papers, holds 22 U.S patents, and has presented several invited talks and tutorials in these areas.

1. R. Venkatesan, V. Kozhikkottu, C. Augustine, A. Raychowdhury, K. Roy, and A. Raghunathan, “TapeCache: a high density, energy efficient cache based on domain wall memory,” Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design (ISLPED ’12), pp. 185-190, 2012.
2. S. Gupta, N. Mojumder, A. Raghunathan, and K. Roy, “Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture,” 49th Design Automation Conference (DAC), pp. 492-497, 2012.
3. S. Venkataramani, A. Sabne, V. Kozhikkottu, K. Roy, and A. Raghunathan, “SALSA: systematic logic synthesis of approximate circuits,” DAC '12 Proceedings of the 49th Annual Design Automation Conference, pp. 796-801, 2012.