Sachin S. Sapatnekar
Dr. Sapatnekar currently is the Henle Chair in ECE and the Distinguished McKnight University Professorship at the University of Minnesota. He received his PhD from the University of Illinois at Urbana-Champaign in 1992. He is a recipient of the NSF Career Award, seven best paper awards at various conferences, and the SRC Technical Excellence award. He is a fellow of the IEEE. He served on the Executive Committee of the ACM/IEEE Design Automation Conference (DAC) from 2005-2011, including as General Chair in 2010, and is currently Editor-in-Chief of the IEEE Transactions on CAD. His research interests are in the area of design automation of integrated systems, an area in which he has published widely.
|1.||P. Zhou, W. H. Choi, B. Kim, C. H. Kim, and S. S. Sapatnekar, “Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2012 (to appear).|
|2.||A. Paul, M. Amrein, S. Gupta, A. Vinod, A. Arun, S. Sapatnekar, and C. H. Kim, “Staggered Core Activation: A Circuit/Architectural Approach for Mitigating Resonant Supply Noise Issues in Multi-core Multi-power Domain Processors,” Proceedings of the IEEE Custom Integrated Circuits Conference, 2012.|
|3.||Y. Wei, C. Sze, N. Viswanathan, Z. Li, C. J. Alpert, L. Reddy, A. D. Huber, G. E. Tellez, D. Keller, and S. S. Sapatnekar, “GLARE: Global and local wiring aware routability evaluation,” Proceedings of the ACM/EDAC/IEEE Design Automation Conference, pp. 768 – 773, 2012.|
|4.||J. Yin, P. Zhou, A. Holey, S. S. Sapatnekar, and A. Zhai, “Energy-efficient non-minimal path onchip interconnection network for heterogeneous systems,” Proceedings of the IEEE International Symposium on Low Power Electronics and Design, 2012.|
|5.||P. Zhou, D. Jiao, C. H. Kim, and S. S. Sapatnekar, “Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network,” Proceedings of the IEEE Custom Integrated Circuits Conference, 2011.
|6.||S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, “Adaptive techniques for overcoming performance degradation due to aging in CMOS circuits,” IEEE Trans. VLSI Sys. 19, 603 (2011).|
|7.||Q. Liu and S. S. Sapatnekar, “Capturing post-silicon variations using a representative critical path,” IEEE Trans. Computer-Aided Design of Int. Circ. and Sys. 29, 211 (2010).|
|8.||J.-L. Tsai, C. C.-P. Chen, G. Chen, B. Goplen, H. Qian, Y. Zhan, S.-M. Kang, D.-F. Wong, and S. S. Sapatnekar, “Temperature-aware placement for SOCs,” Proc. IEEE 94, 1502 (2006).|