University of Minnesota

Steven J. Koester is a Professor in the Department of Electrical and Computer Engineering at the University of Minnesota. Dr. Koester received his Ph.D. in 1995 from the University of California, Santa Barbara. From 1997 to 2010 he was a research staff member at the IBM T. J. Watson Research Center and made significant contributions to the development of strained Si and SiGe MOSFETs [1-2], Ge photodetectors [3] and III-V MOSFETs [4]. From 2006-2010 he served as manager of Exploratory Technology at IBM Research where his team investigated advanced devices and integration concepts for use in future generations of microprocessor technology [5-7]. Since joining the University of Minnesota in 2010, his research has focused on novel device concepts, with an emphasis on graphene devices [8-9]. He currently is collaborating with Jian-Ping Wang, Chris Kim, and Paul Crowell to investigate spin-based logic using graphene interconnects, and has demonstrated a process to transfer graphene onto patterned substrates [8-9], which has advantages for integration with magnetic materials, particularly MTJs. Dr. Koester has authored or co-authored over 150 technical publications and conference presentations, 3 book chapters, edited 6 volumes, and holds 36 United States patents. He is a senior member of IEEE and is an associate editor for IEEE Electron Device Letters.

1.	K. Rim, S. Koester, M. Hargrove, J. Chu, P. M. Mooney, J. Ott, T. Kanarsky, P. Ronsheim, M. Ieong, A. Grill, and H.-S. P. Wong, “Strained Si NMOSFETs for high performance CMOS technology,” Proceedings of the 2001 Symposium on VLSI Technology, Kyoto, Japan, Jun. 12-14, 2001.
2.	S. J. Koester, R. Hammond, J. O. Chu, “Extremely high transconductance Ge/Si0.4Ge0.6 pMODFET's grown by UHV-CVD,” IEEE Elect. Dev. Lett. 21, 110 (2000).
3.	S. J. Koester, J. D. Schaub, G. Dehlinger, and J. O. Chu, “Ge-on-SOI infrared detectors for integrated photonic applications,” IEEE J. Sel. Top. Quant. Electron. 12, 1489 (2006).
4.	S. J. Koester, E. W. Kiewra, Y. Sun, D. A. Neumayer, J. A. Ott, M. Copel, D. K. Sadana, D. J. Webb, J. Fompeyrine, J.-P. Locquet, C. Marchiori, M. Sousa, and R. Germann, “Evidence of electron and hole inversion in GaAs MOS capacitors with HfO2 gate dielectrics and a-Si/SiO2 interlayers,” Appl. Phys. Lett. 89, 042104 (2006).
5.	S. O. Koswatta, S. J. Koester, and W. Haensch, “On the possibility of obtaining MOSFET-like performance and sub-60-mV/dec swing in 1-D broken-gap tunnel transistors,” IEEE Trans. Elect. Dev. 57, 3222 (2010).
6.	A. Majumdar, Z. Ren, A. Kumar, D. R. Greenberg, C. Wang, T. N. Adam, K. Barker, J. Chang, D. Dobuzinsky, O. Gluschenkov, J. R. Holt, K. Maitra, R. T. Mo, G. Pei, J. Sleight, R. Venigalla, C. Ouyang, S. J. Koester, and W. Haensch, “Undoped-body 8nm-thin silicon-on-insulator field-effect transistors,” IEEE Elect. Dev. Lett. 29, 515 (2008).
7.	S. J. Koester, A. M. Young, R. R. Yu, S. Purushothaman, K. N. Chen, D. C. La Tulipe, N. Rana, L. Shi, M. R. Wordeman, and E. J. Sprogis, “Wafer-level three-dimensional integration technology,” IBM J. Res. Dev. 52, 583 (2008).
8.	M. A. Ebrish, H. Shao, and S. J. Koester, “Operation of multi-finger graphene quantum capacitance varactors using planarized local bottom gate electrodes,” Appl. Phys. Lett. 100, 143102 (2012).
9.	S. J. Koester and M. Li, “High-speed waveguide-coupled graphene-on-graphene optical modulators,” Appl. Phys. Lett. 100, 171107 (2012).