Chris H. Kim

Chris Kim photo

Dr. Kim is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Minnesota. His group has expertise in digital, mixed-signal, and memory circuit design in silicon and beyond-silicon (e.g. flextronics, and spintronics) technologies. He spent a year at Intel Corporation prior to joining the University of Minnesota where he performed research on low power circuit techniques and on-chip leakage current monitors. He is the recipient of an NSF CAREER Award, a McKnight Land-Grant Professorship, 3M Non-Tenured Faculty Awards, IBM Faculty Partnership Awards, and an IEEE Circuits and Systems Society Outstanding Author Award. Dr. Kim has extensive experience in both CMOS circuit design and novel circuit architectures. He has made significant contributions in the area of reliability-aware aging-tolerant circuit designs [1-2], and robust low-voltage analog and mixed-signal circuits [3-4]. Dr. Kim also has several ongoing projects involving the circuit design using novel devices [5-7] and materials including organic TFT circuits, and computation using non-silicon circuit elements including spintronic devices.

1. J. Keane, W. Zhang, and C. H. Kim, “An array-based odometer system for statistically significant circuit aging characterization,” IEEE J. of Solid-State Circ. 46, 2374 (2011).
2. Q. Tang, X. Wang, J. Keane, C. H. Kim, "RTN Induced Frequency Shift Measurements Using a Ring Oscillator Based Circuit", VLSI Technology Symposium, Jun. 2013.
3. D. Jiao and C.H. Kim, “A programmable adaptive phase-shifting PLL for enhancing clock data compensation under resonant supply noise,” International Solid-State Circuits Conference (ISSCC), Feb. 2011.
4. B. Kim, W. Xu, C.H. Kim, "A Fully-Digital Beat-Frequency Based ADC Achieving 37dB SNDR for a 1.6mVpp Input Signal", Custom Integrated Circuits Conference (CICC), Sep. 2013.
5. W. Zhang, M. Ha, D. Braga, M. Renn, C. D. Frisbie, and C. H. Kim, “A 1V printed organic DRAM cell based on ion-gel gated transistors with a sub-10nW-per-cell refresh power,” International Solid-State Circuits Conference (ISSCC), Feb. 2011.
6. M. Ha, X. Yu, A. Green, W. Zhang, M. Renn, C. H. Kim, M. Hersam, and C. D. Frisbie, “Printed, Sub-3 V digital circuits on plastic from aqueous carbon nanotube inks,” ACS Nano 4, 4388 (2010).
7. K. Chun, H. Zhao, J. D. Harms, T. Kim, J. P. Wang, C. H. Kim, "A Scaling Roadmap and Performance Evaluation of In-plane and Perpendicular MTJ Based STT-MRAMs for High-density Cache Memory", IEEE Journal of Solid-State Circuits (JSSC), Feb. 2013